The primary performance objective for a power MOSFET switch is the achievement of the lowest possible on-resistance for a given breakdown voltage rating. The breakdown voltage is a measure of the ability of the MOSFET to withstand voltage when it is turned off, and the on-resistance is a measure of the ability of the MOSFET to carry a current with a minimal loss of power when it is turned on. The on-resistance is defined as the ratio of drain-to-source voltage to drain current when the switch is turned on.
Structurally, power MOSFETs fall into two main categories. In lateral MOSFETs, the current flow is primarily "lateral" between source and drain regions that are formed at the surface of the substrate. In vertical MOSFETs, the current flow is primarily "vertical" between a source region located at the top surface of the substrate and a drain region located adjacent the backside of the substrate. In one subcategory of vertical MOSFETs, the gate is formed in a trench which extends into the top surface of the substrate. A trench-gated MOSFET is exemplified in the cross-sectional view of FIG. 1, which shows a MOSFET 10 having an N+ source region 11, a drain region 12 which includes an N++ substrate 13 and an N-epitaxial (epi) layer 14, and a P-body region 15. Current flows between source region 11 and drain region 12 through a channel in P-body region 15 adjacent the side wall of trenched gate 16. Viewed from above, the trench appears as a pattern which divides the MOSFET into geometric cells. The cells may be rectangular, square, hexagonal or some other shape. A planar double-diffused MOSFET is exemplified by MOSFET 20 shown in FIG. 2, having an N+ source region 21, a drain region 22 which includes an N++ substrate 23 and an N-epi layer 24, and a P-body region 25. Current flows between source region 21 and drain region 22 through a channel in P-body region 25 directly under a gate 26.
In both of MOSFETs 10 and 20 the body regions (15,25) are normally biased to a fixed potential. In particular, metal layers 17,27 short the body regions to the source regions (11,21) through P+ body contact regions 18,28. Body regions 15,25 are doped with P-type ions to the point that neither body region becomes completely depleted, even at high drain-to-source or gate-to-drain potentials. Because the body regions are not depleted and are always shorted to the source regions, the voltage applied to MOSFETs 10,20 when they are turned off appears across the drain-to-body junction. A depletion region forms around the drain-to-body junction, mostly on the more lightly doped drain side of the junction.
FIG. 3A is a view of a portion of MOSFET 10 along cross-section III--III shown in FIG. 1, and FIG. 3B shows a profile of the dopant concentration along cross-section III--III at a drain voltage of zero. The depletion regions surrounding the source-to-body junction S/B and the drain-to-body junction D/B are shown in FIG. 3B. The corresponding energy bands are shown in FIG. 3C, which displays a conduction band E.sub.c, a valence band E.sub.v, and an intrinsic level E.sub.i, along with the Fermi level E.sub.f in equilibrium. The source-to-body junction creates a built-in energy barrier which prevents electrons from flowing from the source to the drain. FIG. 3D is a similar energy band diagram which shows only the conduction band E.sub.c. The energy barrier between the source and body is clearly evident. Finally, FIG. 3E shows the changes in the conduction band as the voltage at the drain is progressively raised to a level V.sub.D1 &gt;0 and then to a level V.sub.D2 &gt;V.sub.D1. Since the body region is not fully depleted, as shown in FIG. 3B, the application of a reverse bias between the drain and body does not lower the source-body barrier height. Thus MOSFET 10 avoids a punchthrough condition (where the depletion regions around the source-body and drain-body junctions meet) by preventing its body region from becoming completely depleted and maintaining its built-in source-to-body energy barrier at all levels of the drain voltage. This property is characteristic of a long-channel MOSFET.
As shown in the equivalent circuit diagram of FIG. 4, because the source and body regions of MOSFET 10 are shorted together, the PN diode represented by the drain-to-body junction appears "anti-parallel", i.e., parallel to the normal path of current through MOSFET 10 (from the drain to the source) but opposite in direction. The disadvantage of having the source-body short in MOSFET 10 is a loss of bidirectional current blocking capability and in some applications unwanted PN diode conduction, which can lead to charge storage near the drain-body junction, large reverse recovery times, ringing, etc. FIG. 4 shows that a parasitic bipolar transistor also resides within MOSFET 10, having a base region represented by the undepleted body region of the MOSFET. Unless precautions are taken, this parasitic bipolar transistor can produce undesirable operating conditions.
Despite these disadvantages, the source-to-body short is generally needed in conventional MOSFETs for several reasons. First and foremost, the body region must have a well-defined potential in order to prevent the threshold voltage of the MOSFET from drifting upward and downward uncontrollably. For example, if the source-body junction were to become reverse-biased, as a result of the well-known "body effect" the threshold voltage of the device would tend to increase. Second, the source-body short is needed to prevent snapback in the parasitic bipolar transistor, an undesirable phenomenon which leads to a substantial reduction of the off-state breakdown voltage of the device (referred to as BV.sub.ceo breakdown in bipolar transistors). This problem is especially acute for MOSFETs having design breakdown voltages over 30 V, since the snapback voltage of the parasitic bipolar transistor may be only 10 or 20 V. Operating at 500 V and snapping back to 20 V, for example, would lead to destructive currents in the device.
A major disadvantage of having an integral source-body short is that it must be included in every vertical MOSFET cell, thereby wasting valuable area and requiring a larger cell pitch. A larger cell pitch results in fewer cells and a lower total gate width per unit area, which in turn increases the on-resistance of the MOSFET. For example, as shown in FIGS. 5A and 5B, the minimum width of the source-body short region for a planar DMOSFET and a trenched-gate MOSFET, respectively, is about 4 .mu.m. In the planar DMOSFET, where the length of the gate is limited to at least around 4 .mu.m, this implies a minimum cell pitch of 8 .mu.m, and even in the trenched-gate MOSFET the source-body short limits the cell pitch to about 5 .mu.m.
Two types of trenched-gate MOSFETs have been proposed to eliminate the need for a source-body short. One type, known as an accumulation mode FET or ACCUFET, is shown in cross-section in FIG. 6. ACCUFET 60 is a trenched-gate device which uses a semiconductor material of a single conductivity type but in different doping concentrations. Its gate is doped with P-type material such that the lightly-doped N-region 61 is fully depleted when the gate is turned off. Accordingly, the ACCUFET's leakage characteristic is that of a device which relies on an electrically induced potential barrier created by the gate rather than the built-in voltage of a PN junction.
FIG. 7A shows a portion of ACCUFET 60 taken at cross-section VII--VII in FIG. 6. FIGS. 7B and 7C show the doping concentration profile and energy bands, respectively, at cross-section VII--VII. The influence of the gate in forming an energy barrier is evident from FIG. 7C, where the intrinsic level E.sub.i in the lightly doped region 61 is below the Fermi level (i.e., N-type) without the assistance of the gate but crosses the Fermi level (acting like an electrically-induced P-type region) when the gate is driven high. FIG. 7D shows that the energy barrier is almost immediately lowered by the application of any drain-to-source bias V.sub.D. The ACCUFET is further described in application Ser. No. 08/459,054, filed Jun. 2, 1995.
The second type of device, sometimes referred to as a punchthrough FET or PT-FET, is illustrated in cross-section in FIG. 8. PT-FET 80 includes a P-body region 81 which is of opposite conductivity type to its N+ source region 82 and N+ drain region 83. Unlike a conventional MOSFET, however, the gate 84 is doped with P-type material, and the "mesa" between the gate trenches is made narrow. Moreover, the doping of P-body region 81 is so light that any small amount of drain voltage V.sub.D fully depletes the body region. This is evident from FIGS. 9B and 9C, which show the doping profile at cross-section IX--IX in FIG. 8 when V.sub.D equals 0 V and 0.1-1.0 V, respectively. Note from FIG. 9B that only a small portion of the body region 81 remains undepleted at V.sub.D =0 V and, as shown in FIG. 9C, the body region is fully depleted when V.sub.D =0.1-1.0 V. Since the body region is fully depleted, it does not float, and no external body bias is required to define and stabilize the threshold voltage. There is no "quasi neutral" region in the P-body in which to apply an externally defined body bias. In this way the problem of threshold voltage drift is avoided.
In its off-state, then, the PT-FET relies on the effect of the P-type gate on the P-type body material in the narrow mesa between the gate trenches to increase the height of the energy barrier between the source and body regions and thereby minimize its leakage current. The gate does not materially affect the depletion of the P-body region. Depletion spreading in the P-body region occurs almost entirely as a result of the PN junctions between the body region and the source and drain regions, respectively.
As shown in FIG. 9D, however, the fact that the body region is fully depleted at small levels of V.sub.D means that, despite the P-type gate and narrow mesa, drain-induced barrier lowering (DIBL) occurs at small levels of V.sub.D. DIBL gives rise to a diffusion current which has a maximum limit determined by the charge carrier velocity. Thus in some situations the PT-FET may suffer from an unacceptably high leakage current.
The PT-FET is further described in application Ser. No. 08/415,009, filed Mar. 31, 1995, now U.S. Pat. No. 5,592,005, issued Jan. 7,1997.